£47k – £63k per annum
Job Details:
Digital Verification Engineer- UVM / SystemVerilogWe are partnered up with a well-established Global Semiconductor organisation who are looking for Digital Verification Engineers to join their team in the United Kingdom/Cambridge.If this is you please continue reading below!Responsibilities:UVM and SystemVerilog-based Digital Verification environment definition and development
Define VIP’s integration into the Project’s Digital Verification environment as well as its standardization, development, and documentation
Define and design Digital Verification Top-Level Tests.
Digital Verification estimation, planning, and scheduling to meet tape-out datesRelocation and visa sponsorship is availableQualifications:BS/MS in Electrical Engineering
Good knowledge in Digital Verification Languages – UVM and System Verilog
Strong experience in both RTL and Gate-Level Verification
Experience in System Verilog, UVM, Verilog, and C/C++ is required.
Previous verification experience in test planning, scripting, simulation, and problem-solving.Keywords: UVM / GPU /System Verilog / Verilog / C / C++ / Emulation / RTL / ASIC / Design Verification
